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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1994 copyright ? intel corporation, 1995 order number: 272145-003 8xc196kd/8xc196kd20 commercial chmos microcontroller 87c196kde32 kbytes of on-chip otprom 83c196kde32 kbytes of rom y 16 mhz and 20 mhz available y 1000 byte register ram y register-to-register architecture y 28 interrupt sources/16 vectors y peripheral transaction server y 1.4 m s 16 x 16 multiply (20 mhz) y 2.4 m s 32/16 divide (20 mhz) y powerdown and idle modes y five 8-bit i/o ports y 16-bit watchdog timer y dynamically configurable 8-bit or 16-bit buswidth y full duplex serial port y high speed i/o subsystem y 16-bit timer y 16-bit up/down counter with capture y 3 pulse-width-modulated outputs y four 16-bit software timers y 8- or 10-bit a/d converter with sample/hold y hold /hlda bus protocol y otp one-time programmable version the 8xc196kd 16-bit microcontroller is a high performance member of the mcs 96 microcontroller family. the 8xc196kd is an enhanced 80c196kc device with 1000 bytes ram, 16 mhz operation and an optional 32 kbytes of rom/eprom. intel's chmos iii process provides a high performance processor along with low power consumption. the 8xc196kd has a maximum guaranteed frequency of 16 mhz. the 8xc196kd20 has a maximum guaran- teed frequency of 20 mhz. unless otherwise noted, all references to the 8xc196kd also refer to the 8xc196kd20. four high-speed capture inputs are provided to record times when events occur. six high-speed outputs are available for pulse or waveform generation. the high-speed output can also generate four software timers or start an a/d conversion. events can be based on the timer or up/down counter.
8xc196kd/8xc196kd20 272145 1 figure 1. 8xc196kd block diagram 87c196kd enhanced feature set over the 87c196kc 1. the 87c196kd has twice the ram and twice the otprom space of the 87c196kc. 2. the vertical windowing scheme has been extend- ed to allow all 1000 bytes of register ram to be windowed into the lower register file. ioc3 (0ch hwin1 read/write) 272145 2 note: * rsvereserved bits must be e 0 figure 2. 87c196kd new sfr bit (clkout disable) 2
8xc196kd/8xc196kd20 8xc196kd vertical windowing map table 1. 128-byte windows address to device wsr contents remap series 0380h kd x001 0111b e 17h 0300h kd x001 0110b e 16h 0280h kd x001 0101b e 15h 0200h kd x001 0100b e 14h 0180h kc, kd x001 0011b e 13h 0100h kc, kd x001 0010b e 12h 0080h kc, kd x001 0001b e 11h 0000h kc, kd x001 0000b e 10h window in lower register file: 80h ffh table 2. 64-byte windows address to device wsr contents remap series 03c0h kd x010 1111b e 2fh 0380h kd x010 1110b e 2eh 0340h kd x010 1101b e 2dh 0300h kd x010 1100b e 2ch 02c0h kd x010 1011b e 2bh 0280h kd x010 1010b e 2ah 0240h kd x010 1001b e 29h 0200h kd x010 1000b e 28h 01c0h kc, kd x010 0111b e 27h 0180h kc, kd x010 0110b e 26h 0140h kc, kd x010 0101b e 25h 0100h kc, kd x010 0100b e 24h 00c0h kc, kd x010 0011b e 23h 0080h kc, kd x010 0010b e 22h 0040h kc, kd x010 0001b e 21h 0000h kc, kd x010 0000b e 20h window in lower register file: c0h ffh table 3. 32-byte windows address to device wsr contents remap series 03e0h kd x101 1111b e 5fh 03c0h kd x101 1110b e 5eh 03a0h kd x101 1101b e 5dh 0380h kd x101 1100b e 5ch 0360h kd x101 1011b e 5bh 0340h kd x101 1010b e 5ah 0320h kd x101 1001b e 59h 0300h kd x101 1000b e 58h 02e0h kd x101 0111b e 57h 02c0h kd x101 0110b e 56h 02a0h kd x101 0101b e 55h 0280h kd x101 0100b e 54h 0260h kd x101 0011b e 53h 0240h kd x101 0010b e 52h 0220h kd x101 0001b e 51h 0200h kd x101 0000b e 50h 01e0h kc, kd x100 1111b e 4fh 01c0h kc, kd x100 1110b e 4eh 01a0h kc, kd x100 1101b e 4dh 0180h kc, kd x100 1100b e 4ch 0160h kc, kd x100 1011b e 4bh 0140h kc, kd x100 1010b e 4ah 0120h kc, kd x100 1001b e 49h 0100h kc, kd x100 1000b e 48h 00e0h kc, kd x100 0111b e 47h 00c0h kc, kd x100 0110b e 46h 00a0h kc, kd x100 0101b e 45h 0080h kc, kd x100 0100b e 44h 0060h kc, kd x100 0011b e 43h 0040h kc, kd x100 0010b e 42h 0020h kc, kd x100 0001b e 41h 0000h kc, kd x100 0000b e 40h window in lower register file: e0h ffh 3
8xc196kd/8xc196kd20 process information this device is manufactured on px29.5 or px29.9, a chmos iii process. additional process and reliabili- ty information is available in intel's components quality and reliability handbook, order number 210997. 272145 19 example: n87c196kd20 is 68-lead plcc otprom, 20 mhz. for complete package dimensional data, refer to the intel packaging handbook (order number 240800). note: 1. eproms are available as one time programmable (otprom) only. figure 3. the 8xc196kd family nomenclature table 4. thermal characteristics package i ja i jc type plcc 35 c/w 13 c/w qfp 56 c/w 12 c/w sqfp 68 c/w 15.5 c/w all thermal impedance data is approximate for static air conditions at 1w of power dissipation. values will change depending on operation conditions and application. see the intel packaging handbook (order number 240800) for a description of intel's thermal impedance test methodology. table 5. 8xc196kd memory map description address external memory or i/o 0ffffh 0a000h internal rom/otprom or external 9fffh memory (determined by ea ) 2080h reserved. must contain ffh. 207fh (note 5) 205eh pts vectors 205dh 2040h upper interrupt vectors 203fh 2030h rom/otprom security key 202fh 2020h reserved. must contain ffh. 201fh (note 5) 201ah reserved. must contain 20h 2019h (note 5) ccb 2018h reserved. must contain ffh. 2017h (note 5) 2014h lower interrupt vectors 2013h 2000h port 3 and port 4 1fffh 1ffeh external memory 1ffdh 0400h 1000 bytes register ram (note 1) 03ffh 0018h cpu sfr's (notes 1, 3) 0017h 0000h notes: 1. code executed in locations 0000h to 03ffh will be forced external. 2. reserved memory locations must contain 0ffh unless noted. 3. reserved sfr bit locations must contain 0. 4. refer to 8xc196kc for sfr descriptions. 5. warning: reserved memory locations must not be written or read. the contents and/or function of these lo- cations may change with future revisions of the device. therefore, a program that relies on one or more of these locations may not function properly. 4
8xc196kd/8xc196kd20 272145 3 figure 4. 68-pin plcc package 5
8xc196kd/8xc196kd20 272145 4 note: n.c. means no connect (do not connect these pins). figure 5. 80-pin qfp package 6
8xc196kd/8xc196kd20 272145 20 note: n.c. means no connect (do not connect these pins). figure 6. 80-pin sqfp package 7
8xc196kd/8xc196kd20 pin descriptions symbol name and function v cc main supply voltage (5v). v ss digital circuit ground (0v). there are multiple v ss pins, all of which must be connected. v ref reference voltage for the a/d converter (5v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . v pp timing pin for the return from powerdown circuit. this pin also supplies the programming voltage on the eprom device. xtal1 input of the oscillator inverter and of the internal clock generator. xtal2 output of the oscillator inverter. clkout output of the internal clock generator. the frequency of clkout is (/2 the oscillator frequency. reset reset input and open drain output. buswidth input for buswidth selection. if ccr bit 1 is a one, this pin selects the bus width for the bus cycle in progress. if buswidth is a 1, a 16-bit bus cycle occurs. if buswidth i sa0an 8-bit cycle occurs. if ccr bit 1 is a 0, the bus is always an 8-bit bus. nmi a positive transition causes a vector through 203eh. inst output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is activated only during external memory accesses and output low for a data fetch. ea input for memory select (external access). ea equal high causes memory accesses to locations 2000h through 9fffh to be directed to on-chip rom/eprom. ea equal low causes accesses to those locations to be directed to off-chip memory. also used to enter programming mode. ale/adv address latch enable or address valid output, as selected by ccr. both pin options provide a signal to demultiplex the address from the address/data bus. when the pin is adv , it goes inactive high at the end of the bus cycle. ale/adv is activated only during external memory accesses. rd read signal output to external memory. rd is activated only during external memory reads. wr /wrl write and write low output to external memory, as selected by the ccr. wr will go low for every external write, while wrl will go low only for external writes where an even byte is being written. wr /wrl is activated only during external memory writes. bhe /wrh bus high enable or write high output to external memory, as selected by the ccr. bhe will go low for external writes to the high byte of the data bus. wrh will go low for external writes where an odd byte is being written. bhe /wrh is activated only during external memory writes. ready ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. when the external memory is not being used, ready has no effect. hsi inputs to high speed input unit. four hsi pins are available: hsi.0, hsi.1, hsi.2 and hsi.3. two of them (hsi.2 and hsi.3) are shared with the hso unit. hso outputs from high speed output unit. six hso pins are available: hso.0, hso.1, hso.2, hsi.3, hso.4 and hso.5. two of them (hso.4 and hso.5) are shared with the hsi unit. 8
8xc196kd/8xc196kd20 pin descriptions (continued) symbol name and function port 0 8-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. port 1 8-bit quasi-bidirectional i/o port. port 2 8-bit multi-functional port. all of its pins are shared with other functions in the 8xc196kd. pins 2.6 and 2.7 are quasi-bidirectional. ports 3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. hold bus hold input requesting control of the bus. hlda bus hold acknowledge output indicating release of the bus. breq bus request output activated when the bus controller has a pending external memory cycle. pmode determines the eprom programming mode. pact a low signal in auto programming mode indicates that programming is in process. a high signal indicates programming is complete. pale a falling edge in slave programming mode and auto configuration byte programming mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). prog a falling edge in slave programming mode indicates that ports 3 and 4 contain valid programming data (input to slave). pver a high signal in slave programming mode and auto configuration byte programming mode indicates the byte programmed correctly. cpver cummulative program output verification. pin is high if all locations have programmed correctly since entering a programming mode. ainc auto increment. active low input enables the auto increment mode. auto increment allows reading or writing sequential eprom locations without address transactions across the pbus for each read or write. 9
8xc196kd/8xc196kd20 electrical characteristics absolute maximum ratings * ambient temperature under bias b 55 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin to v ss except ea and v pp b 0.5v to a 7.0v (1) voltage from ea or v pp to v ss or angnd b 0.5v to a 13.00v power dissipation 1.5w (2) notes: 1. this includes v pp and ea on rom or cpu only devices. 2. power dissipation is based on package heat transfer lim- itations, not device power consumption. notice: this data sheet contains information on products in the sampling and initial production phases of development. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max units t a ambient temperature under bias commercial temp. 0 a 70 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.00 5.50 v angnd analog ground voltage v ss b 0.4 v ss a 0.4 v (1) f osc oscillator frequency (8xc196kd) 8 16 mhz f osc oscillator frequency (8xc196kd20) 8 20 mhz note: 1. angnd and v ss should be nominally at the same potential. dc characteristics (over specified operating conditions) symbol description min max units test conditions v il input low voltage b 0.5 0.8 v v ih input high voltage (note 1) 0.2 v cc a 1.0 v cc a 0.5 v v hys hysteresis on reset 300 mv v cc e 5.0v v ih1 input high voltage on xtal 1 0.7 v cc v cc a 0.5 v v ih2 input high voltage on reset 2.2 v cc a 0.5 v v ol output low voltage 0.3 v i ol e 200 m a 0.45 v i ol e 2.8 ma 1.5 v i ol e 7ma v ol1 output low voltage 0.8 v i ol ea 0.4 ma in reset on p2.5 (note 2) v oh output high voltage v cc b 0.3 v i oh eb 200 m a (standard outputs) (note 4) v cc b 0.7 v i oh eb 3.2 ma v cc b 1.5 v i oh eb 7ma v oh1 output high voltage v cc b 0.3 v i oh eb 10 m a (quasi-bidirectional outputs) v cc b 0.7 v i oh eb 30 m a (note 3) v cc b 1.5 v i oh eb 60 m a 10
8xc196kd/8xc196kd20 dc characteristics (over specified operating conditions) (continued) symbol description min typ max units test conditions i oh1 logical 1 output current in reset b 0.8 ma v ih e v cc b 1.5v on p2.0. do not exceed this or device may enter test modes. i il2 logical 0 input current in reset b 12.0 ma v in e 0.45v on p2.0. maximum current that must be sunk by external device to ensure test mode entry. i ih1 logical 1 input current. maximum a 200 m av in e 2.4v current that external device must source to initiate nmi. i li input leakage current (std. g 10 m a0 k v in k v cc b 0.3v inputs) (note 5) i li1 input leakage current (port 0) g 3 m a0 k v in k v ref i tl 1 to 0 transition current (qbd b 650 m av in e 2.0v pins) i il logical 0 input current (qbd pins) b 70 m av in e 0.45v i il1 ad bus in reset b 70 m av in e 0.45v i cc active mode current in reset 65 75 ma xtal1 e 16 mhz (8xc196kd) v cc e v pp e v ref e 5.5v i cc active mode current in reset 80 92 ma xtal1 e 20 mhz (8xc196kd20) v cc e v pp e v ref e 5.5v i idle idle mode current (8xc196kd) 17 25 ma xtal1 e 16 mhz v cc e v pp e v ref e 5.5v i idle idle mode current (8xc196kd20) 21 30 ma xtal1 e 20 mhz v cc e v pp e v ref e 5.5v i pd powerdown mode current 8 15 m av cc e v pp e v ref e 5.5v i ref a/d converter reference current 2 5 ma v cc e v pp e v ref e 5.5v r rst reset pullup resistor 6k 65k x v cc e 5.5v, v in e 4.0v c s pin capacitance (any pin to v ss )10pf notes: 1. all pins except reset and xtal1. 2. violating these specifications in reset may cause the part to enter test modes. 3. qbd (quasi-bidirectional) pins include port 1, p2.6 and p2.7. 4. standard outputs include ad0 15, rd ,wr , ale, bhe , inst, hso pins, pwm/p2.5, clkout, reset, ports 3 and 4, txd/p2.0 and rxd (in serial mode 0). the v oh specification is not valid for reset. ports 3 and 4 are open-drain outputs. 5. standard inputs include hsi pins, ready, buswidth, rxd/p2.1, extint/p2.2, t2clk/p2.3 and t2rst/p2.4. 6. maximum current per pin must be externally limited to the following values if v ol is held above 0.45v or v oh is held below v cc b 0.7v: i ol on output pins: 10 ma i oh on quasi-bidirectional pins: self limiting i oh on standard output pins: 10 ma 7. maximum current per bus pin (data and control) during normal operation is g 3.2 ma. 8. during normal (non-transient) conditions the following total current limits apply: port 1, p2.6 i ol :29ma i oh is self limiting hso, p2.0, rxd, reset i ol :29ma i oh :26ma p2.5, p2.7, wr , bhe i ol :13ma i oh :11ma ad0 ad15 i ol :52ma i oh :52ma rd , ale, inst clkout i ol :13ma i oh :13ma 11
8xc196kd/8xc196kd20 272145 5 i cc max e 4.13 c frequency a 9ma i cc typ e 3.50 c frequency a 9ma i idle max e 1.25 c frequency a 5ma i idle typ e 0.88 c frequency a 3ma note: frequencies below 8 mhz are shown for reference only; no testing is performed. figure 7. i cc and i idle vs frequency ac characteristics for use over specified operating conditions. test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16/20 mhz the system must meet these specifications to work with the 80c196kd: symbol description min max units notes t avyv address valid to ready setup 2 t osc b 68 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (note 1) t llyx ready hold after ale low t osc b 15 2 t osc b 40 ns (note 1) t avgv address valid to buswidth setup 2 t osc b 68 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 55 ns (note 2) t rldv rd active to input data valid t osc b 22 ns (note 2) t cldv clkout low to input data valid t osc b 45 ns t rhdz end of rd to input data float t osc ns t rxdx data hold after rd inactive 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. if wait states are used, add 2 t osc * n, where n e number of wait states. 12
8xc196kd/8xc196kd20 ac characteristics (continued) for use over specified operating conditions. test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16/20 mhz the 80c196kd will meet these specifications: symbol description min max units notes f xtal frequency on xtal1 (8xc196kd) 8 16 mhz (note 1) f xtal frequency on xtal1 (8xc196kd20) 8 20 mhz (note 1) t osc i/f xtal (8xc196kd) 62.5 125 ns t osc i/f xtal (8xc196kd20) 50 125 ns t xhch xtal1 high to clkout high or low a 20 a 110 ns t clcl clkout cycle time 2 t osc ns t chcl clkout high period t osc b 10 t osc a 15 ns t cllh clkout falling edge to ale rising b 5 a 15 ns t llch ale falling edge to clkout rising b 20 a 15 ns t lhlh ale cycle time 4 t osc ns (note 4) t lhll ale high period t osc b 10 t osc a 10 ns t avll address setup to ale falling edge t osc b 15 t llax address hold after ale falling edge t osc b 35 ns t llrl ale falling edge to rd falling edge t osc b 30 ns t rlcl rd low to clkout falling edge a 4 a 30 ns t rlrh rd low period t osc b 5 ns (note 4) t rhlh rd rising edge to ale rising edge t osc t osc a 25 ns (note 2) t rlaz rd low to address float a 5ns t llwl ale falling edge to wr falling edge t osc b 10 ns t clwl clkout low to wr falling edge 0 a 25 ns t qvwh data stable to wr rising edge t osc b 23 (note 4) t chwh clkout high to wr rising edge b 5 a 15 ns t wlwh wr low period t osc b 20 ns (note 4) t whqx data hold after wr rising edge t osc b 25 ns t whlh wr rising edge to ale rising edge t osc b 10 t osc a 15 ns (note 2) t whbx bhe , inst after wr rising edge t osc b 10 ns t whax ad8 15 hold after wr rising t osc b 30 ns (note 3) t rhbx bhe , inst after rd rising edge t osc b 10 ns t rhax ad8 15 hold after rd rising t osc b 25 ns (note 3) notes: 1. testing performed at 8 mhz. however, the device is static by design and will typically operate below 1 hz. 2. assuming back-to-back bus cycles. 3. 8-bit bus only. 4. if wait states are used, add 2 t osc * n, where n e number of wait states. 13
8xc196kd/8xc196kd20 system bus timings 272145 6 14
8xc196kd/8xc196kd20 ready timings (one wait state) 272145 7 buswidth timings 272145 8 15
8xc196kd/8xc196kd20 hold /hlda timings symbol description min max units notes t hvch hold setup a 55 ns (note 1) t clhal clkout low to hlda low b 15 a 15 ns t clbrl clkout low to breq low b 15 a 15 ns t halaz hlda low to address float a 15 ns t halbz hlda low to bhe , inst, rd ,wr weakly driven a 20 ns t clhah clkout low to hlda high b 15 a 15 ns t clbrh clkout low to breq high b 15 a 15 ns t hahax hlda high to address no longer float b 15 ns t hahbv hlda high to bhe , inst, rd ,wr valid b 10 a 15 ns t cllh clkout low to ale high b 5 a 15 ns note: 1. to guarantee recognition at next clock. dc specifications in hold description min max units weak pullups on adv ,rd , 50k 250k v cc e 5.5v, v in e 0.45v wr ,wr l, bhe weak pulldowns on ale, inst 10k 50k v cc e 5.5v, v in e 2.4 272145 9 16
8xc196kd/8xc196kd20 maximum hold latency bus cycle type internal execution 1.5 states 16-bit external execution 2.5 states 8-bit external execution 4.5 states external clock drive (8xc196kd) symbol parameter min max units 1/t xlxl oscillator frequency 8 16.0 mhz t xlxl oscillator period 62.5 125 ns t xhxx high time 20 ns t xlxx low time 20 ns t xlxh rise time 10 ns t xhxl fall time 10 ns external clock drive (8xc196kd20) symbol parameter min max units 1/t xlxl oscillator frequency 8 20.0 mhz t xlxl oscillator period 50 125 ns t xhxx high time 17 ns t xlxx low time 17 ns t xlxh rise time 8 ns t xhxl fall time 8 ns external clock drive waveforms 272145 10 17
8xc196kd/8xc196kd20 external crystal connections 272145 13 note: keep oscillator components close to chip and use short, direct traces to xtal1, xtal2 and v ss . when using ceramic crystals, c1 e 20 pf, c2 e 20 pf. when using ceramic resonators consult manufacturer for recommended capacitor values. external clock connections 272145 14 note: * required if ttl driver used. not needed if cmos driver is used. ac testing input, output waveforms 272145 11 ac testing inputs are driven at 2.4v for a logic ``1'' and 0.45v for a logic ``0'' timing measurements are made at 2.0v for a logic ``1'' and 0.8v for a logic ``0''. float waveforms 272145 12 for timing purposes a port pin is no longer floating when a 150 mv change from load voltage occurs, and begins to float when a 150 mv change from the loaded v oh /v ol level occurs; i ol /i oh e g 15 ma. explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: he high le low ve valid xe no longer valid ze floating signals: ae address be bhe ce clkout de data ge buswidth he hold hae hlda le ale/adv bre breq re rd we wr /wrh /wrl xe xtal1 ye ready qe data out 18
8xc196kd/8xc196kd20 ac characteristicseserial porteshift register mode serial port timingeshift register mode (mode 0) symbol parameter min max units t xlxl serial port clock period (brr t 8002h) 6 t osc ns t xlxh serial port clock falling edge 4 t osc b 50 4 t osc a 50 ns to rising edge (brr t 8002h) t xlxl serial port clock period (brr e 8001h) 4 t osc ns t xlxh serial port clock falling edge 2 t osc b 50 2 t osc a 50 ns to rising edge (brr e 8001h) t qvxh output data valid to clock rising edge 2 t osc b 50 ns t xhqx output data hold after clock rising edge 2 t osc b 50 ns t xhqv next output data valid after clock rising edge 2 t osc a 50 ns t dvxh input data setup to clock rising edge t osc a 50 ns t xhdx input data hold after clock rising edge 0 ns t xhqz last clock rising to output float 1 t osc ns waveformeserial porteshift register mode serial port waveformeshift register mode (mode 0) 272145 15 19
8xc196kd/8xc196kd20 a to d characteristics the a/d converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of v ref . 10-bit mode a/d operating conditions symbol description min max units t a ambient temperature commercial temp. 0 a 70 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.00 5.50 v angnd analog ground voltage v ss b 0.40 v cc a 0.40 v t sam sample time 1.0 m s (1) t conv conversion time 10 20 m s (1) f osc oscillator frequency (8xc196kd) 8.0 16.0 mhz f osc oscillator frequency (8xc196kd20) 8.0 20.0 mhz note: 1. the value of ad e time is selected to meet these specifications. 10-bit mode a/d characteristics (over specified operating conditions) parameter typical (1) minimum maximum units * notes resolution 1024 1024 levels 10 10 bits absolute error 0 g 3 lsbs full scale error 0.25 g 0.5 lsbs zero offset error 0.25 g 0.5 lsbs non-linearity 1.0 g 2.0 0 g 3 lsbs differential non-linearity error l b 1 a 2 lsbs channel-to-channel matching g 0.1 0 g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.009 lsb/ c full scale 0.009 lsb/ c differential non-linearity 0.009 lsb/ c off isolation b 60 db 2, 3 feedthrough b 60 db 2 v cc power supply rejection b 60 db 2 input series resistance 750 1.2k x 4 voltage on analog input pin angnd b 0.5 v ref a 0.5 v 5, 6 dc input leakage 0 g 3.0 m a sampling capacitor 3 pf notes: * an ``lsb'' as used here has a value of approxiimately 5 mv. (see embedded microcontrollers and processors handbook for a/d glossary of terms.) 1. these values are expected for most parts at 25 c but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. these values may be exceeded if the pin current is limited to g 2 ma. 6. applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. all conversions performed with processor in idle mode. 20
8xc196kd/8xc196kd20 8-bit mode a/d operating conditions symbol description min max units t a ambient temperature commercial temp. 0 a 70 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.00 5.50 v angnd analog ground voltage v ss b 0.40 v ss a 0.40 v t sam sample time 1.0 m s (1) t conv conversion time 7 20 m s (1) f osc oscillator frequency (8xc196kd) 8.0 16.0 mhz f osc oscillator frequency (8xc196kd20) 8.0 20.0 mhz note: 1. the value of ad e time is selected to meet these specifications. 8-bit mode a/d characteristics (over specified operating conditions) parameter typical (1) minimum maximum units * notes resolution 256 256 levels 8 8 bits absolute error 0 g 1 lsbs full scale error g 0.5 lsbs zero offset error g 0.5 lsbs non-linearity 0 g 1 lsbs differential non-linearity error l b 1 a 1 lsbs channel-to-channel matching g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.003 lsb/ c full scale 0.003 lsb/ c differential non-linearity 0.003 lsb/ c off isolation b 60 db 2, 3 feedthrough b 60 db 2 v cc power supply rejection b 60 db 2 input series resistance 750 1.2k x 4 voltage on analog input pin v ss b 0.5 v ref a 0.5 v 5, 6 dc input leakage 0 g 3.0 m a sampling capacitor 3 pf notes: * an ``lsb'' as used here has a value of approximately 20 mv. (see embedded microcontrollers and processors handbook for a/d glossary of terms). 1. these values are expected for most parts at 25 c but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. these values may be exceeded if pin current is limited to g 2 ma. 6. applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. all conversions performed with processor in idle mode. 21
8xc196kd/8xc196kd20 otprom specifications operating conditions symbol description min max units t a ambient temperature during programming 20 30 c v cc supply voltage during programming 4.5 5.5 v (1) v ref reference supply voltage during programming 4.5 5.5 v (1) v pp programming voltage 12.25 12.75 v (2) v ea ea pin voltage 12.25 12.75 v (2) f osc oscillator frequency during auto and slave 6.0 8.0 mhz mode programming f osc oscillator frequency during 6.0 16.0 mhz run-time programming (8xc196kd) f osc oscillator frequency during 6.0 20.0 mhz run-time programming (8xc196kd20) notes: 1. v cc and v ref should nominally be at the same voltage during programming. 2. v pp and v ea must never exceed the maximum specification, or the device may be damaged. 3. v ss and angnd should nominally be at the same potential (0v). 4. load capacitance during auto and slave mode programming e 150 pf. ac otprom programming characteristics (slave mode) symbol description min max units t shll reset high to first pale low 1100 t osc t lllh pale pulse width 50 t osc t avll address setup time 0 t osc t llax address hold time 100 t osc t pldv prog low to word dump valid 50 t osc t phdx word dump data hold 50 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t plph (1) prog pulse width 50 t osc t phll prog high to next pale low 220 t osc t lhpl pale high to prog low 220 t osc t phpl prog high to next prog low 220 t osc t phil prog high to ainc low 0 t osc t ilih ainc pulse width 240 t osc t ilvh pver hold after ainc low 50 t osc t ilpl ainc low to prog low 170 t osc t phvl prog high to pver valid 220 t osc note: 1. this specification is for the word dump mode. for programming pulses, use the modified quick pulse algorithm. 22
8xc196kd/8xc196kd20 dc otprom programming characteristics symbol description min max units i pp v pp supply current (when programming) 100 ma note: do not apply v pp until v cc is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. otprom programming waveforms slave programming mode data program mode with single program pulse 272145 16 note: p3.0 must be high (``1'') 23
8xc196kd/8xc196kd20 slave programming mode in word dump with auto increment 272145 17 note: p3.0 must be low (``0'') slave programming mode timing in data program with repeated prog pulse and auto increment 272145 18 24
8xc196kd/8xc196kd20 8xc196kc to 8xc196kd design considerations 1. memory map. the 8xc196kd has 1024 bytes of ram/sfrs and 32k of otprom. the extra 512 bytes of ram reside in locations 0200h to 03ffh, and the extra 16 kbytes of otprom re- side in locations 6000h to 9fffh. on the 87c196kc these locations are always external, so kc code may have to be modified to run on the kd. 2. the vertical window scheme has been extended to include all on-chip ram. 3. ioc3.1 controls the clkout signal. this bit must be 0 to enable clkout. 4. the 87c196kd has a different autoprogramming algorithm to support 32k of on-chip otprom. 8xc196kd errata 1. 83c196kd can possibly miss interrupts on p0.7. see techbit mc0893. data sheet revision history this data sheet is valid for devices with a ``d'' and ``e'' at the end of the topside tracking number. data sheets are changed as new device information be- comes available. verify with your local intel sales office that you have the latest version before finaliz- ing a design or ordering devices. the following are important differences between the 272145-002 and 272145-003 data sheets: 1. i il1 specification (logic 0 input current in reset) was misnamed. it is renamed i il2 . 2. t llyv and t llgv were removed. these specifi- cations are not necessary for high-speed system designs. 3. an errata with 83c196kd p0.7 extint was add- ed to the errata section. the following are important differences between the 272145-001 and 272145-002 data sheets: 1. added 20 mhz specifications. 2. added 80-lead sqfp package pinout. 3. changed qfp package i ja to 56 c/w from 42 c/w. 4. changed v hys to 300 mv from 150 mv. 5. changed i cc typical specification at 16 mhz to 65 ma from 50 ma. 6. changed i cc maximum specification at 16 mhz to 75 ma from 70 ma. 7. changed i idle typical specification to 17 ma from 15 ma. 8. changed i idle maximum specification to 25 ma from 30 ma. 9. changed i pd typical specification to 8 m a from 15 m a. 10. added i pd maximum specification. 11. changed t cldv maximum specification to t osc b 45 from t osc b 50. 12. changed t llax minimum specification to t osc b 35 from t osc b 40. 13. changed t chwh minimum specification to b 5 from b 10. 14. changed t rhax minimum specification to t osc b 25 from t osc b 30. 15. changed t halaz maximum specification to a 15 from a 10. 16. changed t halbz maximum specification to a 20 from a 15. 17. added t hahbv maximum specification. 18. changed t sam for 10-bit mode to 1 m s from 3 m s. 19. changed t sam for 8-bit mode to 1 m s from 2 m s. 20. changed i ih1 test condition to v in e 2.4v from 5.5v. 21. changed i ih1 maximum specification to a 200 m a from a 100 m a. 22. removed nmi from list of standard inputs. 23. updated i cc and i idle vs frequency graph. 24. updated note under dc eprom programming characteristics. 25. changed i li1 maximum specification to b 12 ma from b 6 ma. 25

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